Global STC Conference Presentations
GSC Agenda
(Note: If we do not show a link to a presentation yet, it means we have not received permission to post it yet from the presenter.)
| Start | Session | |
| Monday May 14 | Future Trends: A Global Perspective | |
| 9:30 AM | Docking & Interface Working Group breakout session (Zinfandel room) | |
| 11:30 AM | Registration (Atlas Peak room) | |
| 12:00 PM | Lunch (Poolside Courtyard) | |
| 1:00 PM | 1.1 | STC welcome & BoD intro (Syrah & Merlot rooms) |
| 1:08 PM | 1.2 | Conference overview |
| 1:15 PM | 1.3 | Keynote speech - G. Dan Hutcheson (VLSI Research) - From Microchips to Nanochips: How we got here…and…where do we go from here |
| 2:05 PM | 1.4 | ITRS Roadmap: Test Challenges Beyond 2010 - Roger Barth (Intel) |
| 2:40 PM | Break | |
| 3:10 PM | 1.5 | Cost of Ownership - David Jimenez (Wright Williams & Kelly) |
| 3:40 PM | 1.6 | Analysts panel discussion - led by G. Dan Hutcheson. David Egan (Lehman Brothers), Mark FitzGerald (Banc of America Securities), Robert Maire (Needham & Co.) & Michael Winters (Bear, Stearns & Co.) |
| 5:10 PM | Open time for check-in & Table Top set up | |
| 6:00 PM | Reception & Table Tops (Poolside Courtyard) | |
| 7:00 PM | Dinner (Poolside Courtyard) | |
| Tuesday May 15 | Test Challenges, Expectations & Solutions | |
| 8:00 AM | Breakfast & Table Tops (Atlas & Castle Peak rooms) | |
| 9:00 AM | Announcements (Syrah & Merlot rooms) | |
| 9:10 AM | 2.1 | Texas Instruments - Billy Antheunisse (Absent due to illness but submitted a presentation to post) - TI Analog Test Challenges |
| 9:45 AM | 2.2 | Toshiba - Kazuhiro Sawada - User Perspective of Toshiba Semiconductor |
| 10:20 AM | 2.3 | Renesas - Hideyuki Aoki - Renesas Strategy and Expectation of STC |
| 10:55 AM | Break | |
| 11:25 AM | 2.4 | Intel - Jim Neeb - ATE to DUT Interconnect Challenges in Digital Applications |
| 12:00 PM | 2.5 | Infineon - Klaus Luther - Future Trends for the ATE Industry from an IDM's Perspective |
| 12:35 PM | Lunch & Table Tops (Atlas & Castle Peak rooms) | |
| 1:50 PM | 2.6 | FormFactor - Sergio Perez - Challenges of Probing Next Generation SoC |
| 2:25 PM | 2.7 | Verigy - Debbora Ahlgren (Absent due to illness) |
| 3:00 PM | 2.8 | Teradyne - Sten Peeters - Developing Standards while Fostering Innovation |
| 3:35 PM | Break | |
| 4:00 PM | 2.9 | LTX - Steve Wigley - Impact of System in Package: A Total Supply Chain Perspective |
| 4:35 PM | 2.10 | Credence - Itzik Goldberger - Test Challenges in the Consumer Age |
| 5:10 PM | 2.11 | Advantest - Keith Lee - The Test Chip Challenge |
| 5:45 PM | Dinner (Poolside Courtyard) | |
| Wednesday May 16 | Enabling the Ecosystem | |
| 8:00 AM | Breakfast (Atlas & Castle Peak rooms) | |
| 8:45 AM | 3.1 | Docking & Interface WG Overview & Status Update - Florian Putz |
| 9:05 AM | 3.2 | OPENSTAR Solutions WG - Paul Roddy |
| 9:25 AM | 3.3 | Probecard WG Report - Naoya Koiso |
| 9:45 AM | 3.4 | Technical WG - Yuhai Ma |
| 10:05 AM | Break | |
| 10:25 AM | 3.5 | IBM - Sanae Seike - Early Lifecycle Yield Improvement of Nanometer Chips Using Volume Yield Diagnostic Analysis |
| 10:55 AM | 3.6 | University WG - Paul Roddy |
| 11:15 AM | 3.7 | PTIM WG Status Report- Burnell G. West, Ph. D. |
| 11:35 AM | 3.8 | Closing remarks, acknowledgements & raffle |
| 11:50 AM | Adjourn | |
1:30 PM PTIM Working Group breakout session (Zinfandel room)